The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for a bitcell of a non-volatile memory and methods of fabricating such structures.
A magnetic random access memory (MRAM) device provides an embedded non-volatile memory technology in which the memory elements operate based on principles of magnetoresistance. Because its memory elements are non-volatile, the data stored by the MRAM device is retained when unpowered. The MRAM device includes multiple bitcells that are arranged in an array of rows and columns. Each bitcell in the array includes a magnetoresistive memory element and a field-effect transistor that controls access to the magnetoresistive memory element for reading and writing data. Each field-effect transistor may include a gate with a single gate electrode or a gate that includes two gate electrodes. A word line is connected to the gate of the field-effect transistors in each row of the array. The word line may be used to select the field-effect transistors in a column of bitcells for data read and write operations to the related magnetoresistive memory elements.
The magnetoresistive memory element of each bitcell includes a pinned layer and a free layer, each of which holds a magnetization. The magnetization of the pinned layer is fixed in its magnetic orientation, and the magnetization of the free layer can be switched by, for example, the application of a programming current. In particular, the magnetic orientations of the pinned and free layers may be programmed to have either a parallel state that provides a low electrical resistance across the layers (“0” state) or an antiparallel state that provides a high electrical resistance across the layers (“1” state).
In a bitcell with a one-transistor one-memory element design, each individual field-effect transistor may include a gate having two gate electrodes arranged in a two contacted (poly) pitch (2CPP) layout or a gate with a single gate electrode in a 1.5CPP layout. As the gate pitch is scaled in connection with advanced technology nodes, a dimension of the field-effect transistor for the bitcell shrinks. However, the back-end-of-line metal stack required for the magnetoresistive memory element cannot be commensurately shrunk to match the scaling of the gate pitch. Due to this process limitation, the one-transistor one-memory element design for the bitcell may become non-manufacturable or, at the least, may have a comparatively large rectangular footprint. In addition, the magnetoresistive memory element is arranged with a significant offset from the center of the bitcell in conventional 2CPP or 1.5CPP layouts. In particular, the magnetoresistive memory element is placed proximate to an outer boundary of the bitcell, which may hinder design options for the bitcell.
Improved structures for a bitcell of a non-volatile memory and methods of fabricating such bitcell structures are needed.